The present invention relates generally to three dimensional (3D) integrated circuits, and more particularly to 3D integrated circuits with through silicon vias and the process by which integrated circuits are bonded together.
Since the invention of the integrated circuit, the semiconductor industry has experienced continual rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing for the integration of more components into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit resistance-capacitance (RC) delay and power consumption increase.
Three-dimensional integrated circuits are therefore created to resolve the above-discussed limitations. In a typical formation process of 3D integrated circuits, two wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. Deep vias are then formed to interconnect devices on the first and second wafers.
Much higher device density has been achieved using 3D integrated circuit technology. As a result, the total wire length is significantly reduced. The number of vias is also reduced. Accordingly, 3D integrated circuit technology has the potential of being the mainstream technology of the next generation.
Various 3D integrated circuits have been proposed by Enquist et al. U.S. Patent Application Publication 2007/0037379 and Morrow et al. U.S. Pat. No. 7,056,813, the disclosures of which are incorporated by reference herein, disclose forming backside through via connections.
Various solutions have been proposed for joining of the metal layers of integrated circuit devices. Reif et al. U.S. Pat. No. 7,307,003, the disclosure of which is incorporated by reference herein, discloses the joining of multiple semiconductor structures wherein the backside of one structure is joined to the front side of another structure by a metallic layer, at least part of which forms an electrical connection in the joined multiple semiconductor structures. The metallic layer also does not extend entirely across the wafer as there are breaks between the part which forms an electrical connection and the remaining parts of the metallic layer.
Hatano et al. U.S. Pat. No. 6,824,888, the disclosure of which is incorporated by reference herein, discloses metal to metal bonding where one metal is beryllium and the other is copper.
Moriceau et al. U.S. Patent Application Publication 2008/0041517 and Beyne et al. U.S. Patent Application Publication 2006/0292824, the disclosures of which are incorporated by reference herein, disclose the joining of electronic substrates by an intermediate bond layer.